HAAR=DISABLED, IDPU=PULL_UP_OFF_THE_ID_, HABA=DISABLED_, ID=A_DEVICE
OTG status and control
| VD | VBUS_Discharge Setting this bit to 1 causes VBUS to discharge through a resistor. |
| VC | VBUS_Charge Setting this bit to 1 causes the VBUS line to be charged. This is used for VBUS pulsing during SRP. |
| HAAR | Hardware assist auto_reset 0 (DISABLED): Disabled 1 (ENABLE_AUTOMATIC_RES): Enable automatic reset after connect on host port. |
| OT | OTG termination This bit must be set to 1 when the OTG controller is in device mode. This controls the pull-down on USB_DM. |
| DP | Data pulsing Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data pulsing during SRP. |
| IDPU | ID pull-up. This bit provides control over the pull-up resistor. 0 (PULL_UP_OFF_THE_ID_): Pull-up off. The ID bit will not be sampled. 1 (PULL_UP_ON_): Pull-up on. |
| HADP | Hardware assist data pulse Write a 1 to start data pulse sequence. |
| HABA | Hardware assist B-disconnect to A-connect 0 (DISABLED_): Disabled. 1 (ENABLE_AUTOMATIC_B_D): Enable automatic B-disconnect to A-connect sequence. |
| ID | USB ID 0 (A_DEVICE): A-device 1 (B_DEVICE): B-device |
| AVV | A-VBUS valid Reading 1 indicates that VBUS is above the A-VBUS valid threshold. |
| ASV | A-session valid Reading 1 indicates that VBUS is above the A-session valid threshold. |
| BSV | B-session valid Reading 1 indicates that VBUS is above the B-session valid threshold. |
| BSE | B-session end Reading 1 indicates that VBUS is below the B-session end threshold. |
| MS1T | 1 millisecond timer toggle This bit toggles once per millisecond. |
| DPS | Data bus pulsing status Reading a 1 indicates that data bus pulsing is detected on the port. |
| RESERVED | reserved |
| IDIS | USB ID interrupt status This bit is set when a change on the ID input has been detected. Software must write a 1 to this bit to clear it. |
| AVVIS | A-VBUS valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-VBUS valid threshold (4.4 V on an A-device). Software must write a 1 to this bit to clear it. |
| ASVIS | A-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the A-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it. |
| BSVIS | B-Session valid interrupt status This bit is set then VBUS has either risen above or fallen below the B-session valid threshold (0.8 V). Software must write a 1 to this bit to clear it. |
| BSEIS | B-Session end interrupt status This bit is set then VBUS has fallen below the B-session end threshold. Software must write a 1 to this bit to clear it. |
| ms1S | 1 millisecond timer interrupt status This bit is set once every millisecond. Software must write a 1 to this bit to clear it. |
| DPIS | Data pulse interrupt status This bit is set when data bus pulsing occurs on DP or DM. Data bus pulsing is only detected when the CM bit in USBMODE = Host (11) and the PortPower bit in PORTSC = Off (0). Software must write a 1 to this bit to clear it. |
| RESERVED | reserved |
| IDIE | USB ID interrupt enable Setting this bit enables the interrupt. Writing a 0 disables the interrupt. |
| AVVIE | A-VBUS valid interrupt enable Setting this bit enables the A-VBUS valid interrupt. Writing a 0 disables the interrupt. |
| ASVIE | A-session valid interrupt enable Setting this bit enables the A-session valid interrupt. Writing a 0 disables the interrupt |
| BSVIE | B-session valid interrupt enable Setting this bit enables the B-session valid interrupt. Writing a 0 disables the interrupt. |
| BSEIE | B-session end interrupt enable Setting this bit enables the B-session end interrupt. Writing a 0 disables the interrupt. |
| MS1E | 1 millisecond timer interrupt enable Setting this bit enables the 1 millisecond timer interrupt. Writing a 0 disables the interrupt. |
| DPIE | Data pulse interrupt enable Setting this bit enables the data pulse interrupt. Writing a 0 disables the interrupt |
| RESERVED | Reserved |